贴片ic：se555dr 品牌ti

features
• timing from microseconds to hours

• adjustable duty cycle
• astable or monostable operation

• ttl-compatible output can sink or source up
to 200 ma

description/ordering information
these devices are precision timing circuits capable of producing accurate time delays or oscillation. in the
time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and
capacitor network. in the astable mode of operation, the frequency and duty cycle can be controlled
independently with two external resistors and a single external capacitor.
the threshold and trigger levels normally are two-thirds and one-third, respectively, of vcc. these levels can be altered by use of the control-voltage terminal. when the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. if the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. the reset (reset) input can override all other inputs and can be used to initiate a new timing cycle. when reset goes low, the flip-flop is reset, and the output goes low. when the output is low, a low-impedance path is provided between discharge (disch) and ground.the output circuit is capable of sinking or sourcing current up to 200 ma. operation is specified for supplies of 5 v to 15 v. with a 5-v supply, output levels are compatible with ttl inputs.