features
■ dsp intellectual property (ip) cores
■ dsp builder interface to the mathworks simulink and matlab
design environment
■ dsp development kit, cyclone ii edition
cyclone ii devices include a powerful fpga feature set optimized for
low-cost applications including a wide range of density, memory,
embedded multiplier, and packaging options. cyclone ii devices support
a wide range of common external memory interfaces and i/o protocols
required in low-cost applications. parameterizable ip cores from altera
and partners make using cyclone ii interfaces and protocols fast and easy.
features the cyclone ii device family offers the following features:
■ high-density architecture with 4,608 to 68,416 les
● m4k embedded memory blocks
● up to 1.1 mbits of ram available without reducing available
logic
● 4,096 memory bits per block (4,608 bits per block including 512
parity bits)
● variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32,
and ×36
● true dual-port (one read and one write, two reads, or two
writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes
● byte enables for data input masking during writes
● up to 260-mhz operation
■ embedded multipliers
● up to 150 18- × 18-bit multipliers are each configurable as two
independent 9- × 9-bit multipliers with up to 250-mhz
performance
● optional input and output registers
■ advanced i/o support
● high-speed differential i/o standard support, including lvds,
rsds, mini-lvds, lvpecl, differential hstl, and differential
sstl
● single-ended i/o standard support, including 2.5-v and 1.8-v,
sstl class i and ii, 1.8-v and 1.5-v hstl class i and ii, 3.3-v pci
and pci-x 1.0, 3.3-, 2.5-, 1.8-, and 1.5-v lvcmos, and 3.3-, 2.5-,
and 1.8-v lvttl
● peripheral component interconnect special interest group (pci
sig) pci local bus specification, revision 3.0 compliance for 3.3-v
operation at 33 or 66 mhz for 32- or 64-bit interfaces
● pci express with an external ti phy and an altera pci express
×1 megacore® function
altera corporation 1–3
february 2008 cyclone ii device handbook, volume 1
introduction
● 133-mhz pci-x 1.0 specification compatibility
● high-speed external memory support, including ddr, ddr2,
and sdr sdram, and qdrii sram supported by drop in
altera ip megacore functions for ease of use
● three dedicated registers per i/o element (ioe): one input
register, one output register, and one output-enable register
● programmable bus-hold feature
● programmable output drive strength feature
● programmable delays from the pin to the ioe or logic array
● i/o bank grouping for unique vccio and/or vref bank
settings
● multivolt™ i/o standard support for 1.5-, 1.8-, 2.5-, and
3.3-interfaces
● hot-socketing operation support
● tri-state with weak pull-up on i/o pins before and during
configuration
● programmable open-drain outputs
● series on-chip termination support
■ flexible clock management circuitry
● hierarchical clock network for up to 402.5-mhz performance
● up to four plls per device provide clock multiplication and
division, phase shifting, programmable duty cycle, and external
clock outputs, allowing system-level clock management and
skew control
● up to 16 global clock lines in the global clock network that drive
throughout the entire device
■ device configuration
● fast serial configuration allows configuration times less than
100 ms
● decompression feature allows for smaller programming file
storage and faster configuration times
● supports multiple configuration modes: active serial, passive
serial, and jtag-based configuration
● supports configuration through low-cost serial configuration
devices
● device configuration supports multiple voltages (either 3.3, 2.5,
or 1.8 v)
■ intellectual property
● altera megafunction and altera megacore function support,
and altera megafunctions partners program (amppsm)
megafunction support, for a wide range of embedded
processors, on-chip and off-chip interfaces, peripheral
functions, dsp functions, and communications functions and
1–4 altera corporation
cyclone ii device handbook, volume 1 february 2008
features
protocols. visit the altera ipmegastore atwww.altera.comto
download ip megacore functions.
● nios ii embedded processor support
the cyclone ii family offers devices with the fast-on feature, which
offers a faster power-on-reset (por) time. devices that support the
fast-on feature are designated with an “a” in the device ordering code.
for example, ep2c5a, ep2c8a, ep2c15a, and ep2c20a. the ep2c5a is
only available in the automotive speed grade. the ep2c8a and ep2c20a
are only available in the industrial speed grade. the ep2c15a is only
available with the fast-on feature and is available in both commercial
and industrial grades. the cyclone ii “a” devices are identical in feature
set and functionality to the non-a devices except for support of the faster
por time.
f cyclone ii a devices are offered in automotive speed grade. for more
information, refer to the cyclone ii section in the automotive-grade device
handbook.
f for more information on por time specifications for cyclone ii a and
non-a devices, refer to the hot socketing & power-on reset chapter in the
cyclone ii device handbook.
table 1–1 lists the cyclone ii device family features. table 1–2 lists the
cyclone ii device package offerings and maximum user i/o pins.