时钟驱动芯片cdc351db

特性

• low output skew, low pulse skew for clock-distribution and clock-generation applications
• operates at 3.3-v v_cc
• lvttl-compatible inputs and outputs
• supports mixed-mode signal operation (5-v input and output voltages with 3.3-v v_cc)
• distributes one clock input to ten outputs
• distributed v_ccand ground pins reduce switching noise
• high-drive outputs (-32-ma i_oh, 32-ma i_ol)
• state-of-the-art epic-iib^tmbicmos design significantly reduces power dissipation
• package options include plastic small-outline (dw) and shrink small-outline (db) packages