features
• only 47 single word instructions
• all instructions are single cycle except for program branches which are two-cycle
• 13-bit wide instructions
• all rom/eprom area goto/fgoto instruction
• all rom/eprom area subroutine call/fcall instruction
• 8-bit wide data path
• 5-level deep hardware stack
• 4k x 13 bits on chip eprom/rom
• 144 x 8 bits on chip general purpose registers (sram)
• operating speed: dc-20 mhz clock input
dc-100 ns instruction cycle
• direct, indirect addressing modes for data accessing
• 8-bit real time clock/counter (timer0) with 8-bit programmable prescaler
• internal power-on reset (por)
• built-in low voltage detector (lvd) for brown-out reset (bor)
• power-up reset timer (pwrt) and oscillator start-up timer(ost)
• on chip watchdog timer (wdt) with internal oscillator for reliable operation and soft-ware watch-dog
enable/disable control
• three i/o ports ioa, iob and ioc with independent direction control
• soft-ware i/o pull-high/pull-down or open-drain control
• one internal interrupt source: timer0 overflow; two external interrupt source: int0 pin, int1 pin
• wake-up from sleep by port b/ioc4/ioc5 input falling
• power saving sleep mode
• programmable code protection
• selectable oscillator options:
- erc: external resistor/capacitor oscillator
- xt: crystal/resonator oscillator
- hf: high frequency crystal/resonator oscillator
- lf: low frequency crystal oscillator
• wide-operating voltage range:
- eprom : 2.3v to 5.5v
- rom : 2.3v to 5.5v |